A Minimal RISC-V Vector Processor for Embedded Systems
Also Available Domains Xilinx Vivado|Xilinx ISE
Objective
This paper presents the first RISC-V vector processor design aimed at microcontrollers that uses the new RISC-V ‘V’ extension for vectors, part of the open-source RISC-V instruction set architecture (ISA).
Abstract
This paper presents the first RISC-V vector processor design aimed at microcontrollers that uses the new RISC-V ‘V’ extension for vectors, part of the open-source RISC-V instruction set architecture (ISA). Being aimed at small embedded devices, it demonstrates a simpler method of parallel execution than traditional vector architectures to minimize logic. It has been synthesized for testing on an FPGA at 50MHz. Typical vector compatible applications have been used as benchmarks. Performance has been improved for the demonstrated applications relative to a comparable scalar RISC-V processor, for an increase in FPGA resource utilization.
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Block Diagram
Specifications
Software Requirements:
· Tool: Xilinx ISE 14.7 /Xilinx Vivado2018.3
· HDL: Verilog
Hardware Requirements:
· Microsoft® Windows XP
· Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support
· 512 MB RAM
· 100 MB of available disk space
Learning Outcomes
- Basics of Digital Electronics
- VLSI design Flow
- Introduction to Verilog Coding
- Different modeling styles in Verilog
o Data Flow modeling
o Structural modeling
o Behavioral modeling
o Mixed level modeling
- Introduction to Arithmetic circuits
- Knowledge on RISC -V vector
- Different control units and instructions
- Knowledge on RISC processor
- Applications in real time
- Xilinx ISE 14.7/Xilinx Vivado2018.3 for design and simulation
- Generation of Netlist
- Solution providing for real time problems
- Project Development Skills:
o Problem Analysis Skills
o Problem Solving Skills
o Logical Skills
o Designing Skills
o Testing Skills
o Debugging Skills
o Presentation Skills
o Thesis Writing Skills
Paper Publishing
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