Also Available Domains Transistor Logic|Cadence EDA
The main aim of this project is to implement the timing error tolerant circuit using time borrow scheme for reducing the setup timing violations generated in the next stage
This paper presents clock controlling technique in flip flops to prevent timing errors. Timing errors are detected and corrected by modify the clock of flip flop without changing the system clock with minimum logics. Timing error is now getting increased attention due to the high rate of error-occurrence on semiconductors. Even slight external disturbance can threaten the timing margin between successive clocks since the latest semiconductor operates with high frequency and small supply voltage. To deal with a timing error, many techniques have been introduced.
Nevertheless, existing methods that mitigate a timing error mostly have time-delaying mechanisms and too complex operation, resulting in a timing problem on clock-based systems and hardware overhead. In this article, we propose a novel timing-error-tolerant method that can correct a timing error instantly through a simple mechanism. By modifying a clock in a flip-flop, the proposed system can recover a timing error without the loss of time in the clock-based system.
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