A Low-Power Low-Voltage Binary Search Analog-to-Digital Converter
Also Available Domains Cadence EDA
Objective
The objective of this project is to design and implement a low-power, low-voltage binary search analog-to-digital converter (ADC) for energy-efficient signal conversion applications. It focuses on achieving high-speed and accurate digital output while minimizing power consumption and operating voltage. The design will be simulated and analyzed to evaluate key performance metrics such as resolution, conversion time, linearity, and power efficiency. Comparative analysis may be conducted to highlight improvements over conventional ADC designs. The overall goal is to develop a compact, high-performance, and low-power ADC suitable for modern portable and low-energy electronic systems.
Abstract
This work presents the design and analysis of a low-power, low-voltage binary-search analog-to-digital converter (ADC), also known as a successive-approximation-type ADC. The proposed ADC is optimized for energy efficiency and minimal supply voltage, making it suitable for battery-powered and portable applications such as sensor nodes and IoT devices. The architecture leverages a binary-search (i.e., successive-approximation) algorithm, using a capacitive DAC, dynamic comparator, and efficient decision logic to minimize switching energy. The converter is implemented in a standard CMOS technology (e.g., 90 nm / 65 nm / chosen node), and simulated under low supply voltage conditions (e.g., ~1 V or lower) to evaluate its performance. Through transient, noise, and corner-case simulations, we assess key metrics such as power consumption, conversion speed (sampling rate), linearity (INL, DNL), signal-to-noise ratio (SNR), and effective number of bits (ENOB). The results demonstrate that the proposed ADC achieves competitive resolution with sub-µW power dissipation, thereby providing a practical solution for power-constrained, low-voltage systems.
NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.
Specifications
ADC Architecture
Binary-search / Successive Approximation (SAR) style
Resolution
e.g., 8-bit or 10-bit (depending on design)
Supply Voltage (VDD)
Low-voltage mode, e.g., 0.8 V–1.2 V (or as per technology)
Sampling Rate
Moderate — e.g., 1 MS/s or more, depending on use-case
DAC Type
Capacitive DAC (CDAC) for binary-weighted voltages
Comparator Type
Low-power, dynamic comparator (e.g., latch-based)
Control / Logic
Successive-approximation register (SAR) logic to do binary search
Power Consumption
Very low: target in µW or tens of µW for core converter
Switching Strategy
Optimized switching to reduce DAC energy (e.g., bottom-plate switching) (MDPI)
Linearity
Low integral non-linearity (INL) and differential non-linearity (DNL), e.g., ±0.5 LSB or better
Noise Performance
High SNR; ENOB close to nominal resolution (depends on comparator noise)
Figure-of-Merit (FoM)
Energy per conversion step target (e.g., fJ / conv-step) — depends on sampling rate & power
Technology / Process
CMOS process node (to be specified, e.g., 65 nm, 130 nm, etc.)
Area / Layout Constraints
Compact layout; minimized capacitor array, small comparator
Learning Outcomes
Understanding the operation of binary search/SAR ADC architecture
Knowledge of comparator design and capacitive DAC operation
Ability to design low-power, low-voltage ADCs
Skills in optimizing transistor sizing for power and accuracy
Understanding trade-offs between speed, resolution, and power
Experience with simulation and waveform analysis of ADC circuits
Insight into layout techniques for low-parasitic, high-accuracy designs
Ability to evaluate ADC performance under process, voltage, and temperature variations
Exposure to energy-efficient VLSI design principles
Paper Publishing
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