A LOW-POWER AND RECONFIGURABLE 16-BIT ADDER USING REVERSIBLE GATES

Project Code :TVMAFE773

Objective

The main objective of this project is to design and implement a low-power, energy-efficient, and reconfigurable 16-bit adder using reversible logic gates. The proposed design aims to minimize power dissipation and heat generation by reducing information loss, which is a fundamental advantage of reversible computing

Abstract

One of the most well-known technologies that is making a bigger contribution to current technological environment is DSP systems. With multiple applications, such as readily transportable electronic gadgets, the system that accepts films and audio as input, etc., embedded systems have gained popularity all over the world. The project is mainly focused on low-power, efficient, and programmable adders. Reversible logic gates, which are mostly employed for designing, provide the basis of this adder. The adders are developed and implemented using the Xilinx tool. These adders can be used in aerospace applications. There was a comparison made between the current and proposed methods in that the proposed way resulted in a reduction of 2005.34 nanowatts compared to the existing method.

Key Words: Field Programmable Gate Array (FPGA), Error Tolerant Adder (ETA), Toffoli gate, Reversible gates,Power Optimization, Reconfigurable , Low Power Adder(LPA).

NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.