A Low-Power and High-Accuracy Approximate Multiplier With Reconfigurable Truncation

In this project, we are going to design approximate multiplier by designing an approximate compressor with high accuracy compared to existing approximate compressors. Multipliers are among the most critical arithmetic functional units in many applications, and those applications commonly require many multiplications which result in significant power consumption. For applications that have error tolerance, employing an approximate multiplier is an emerging method to reduce critical path delay and power consumption. An approximate multiplier can trade off accuracy for lower energy and higher performance. In this paper, we not only propose an approximate 4-2 compressor with high accuracy, but also an adjustable approximate multiplier that can dynamically truncate partial products to achieve variable accuracy requirements. In addition, we also propose a simple error compensation circuit to reduce error distance. The proposed approximate multiplier can adjust the accuracy and power required for multiplications at run-time based on the users’ requirement. Experimental results show that the compared to existing accurate Wallace multiplier, the proposed adjustable approximate multiplier can be reduced in parameter values. The synthesis and simulation of the proposed designs can be implemented using Xilinx ISE 2018.3.