A Low Cost FPGA Implementation of Retinex Based Low Light Image Enhancement Algorithm
Objective
The objective of "A Low Cost FPGA Implementation of Retinex Based Low-Light Image Enhancement Algorithm" is to design and implement a cost-efficient hardware architecture for real-time image enhancement in low-light conditions using the Retinex algorithm. The focus is on leveraging FPGA technology to achieve high processing speed, low hardware resource utilization, and improved visual quality for practical applications in surveillance, automotive vision, and consumer electronics.
Abstract
Low-light conditions pose significant challenges in image processing, often leading to degraded image quality and loss of crucial details. To address this issue, this paper presents a low-cost FPGA implementation of a Retinex-based low-light image enhancement algorithm. The proposed system takes low-light images as input and processes them to generate enhanced images with improved contrast and detail visibility. Implemented in Verilog for hardware compatibility, the algorithm decomposes input images into illumination and reflectance components, applies dynamic range compression, and enhances details for optimal results. Leveraging the parallel processing capabilities of the FPGA, the system achieves real-time performance while maintaining cost-efficiency. Experimental results demonstrate its effectiveness in enhancing low-light images, making it suitable for applications in surveillance, automotive systems, and consumer electronics, highlighting the potential of FPGA-based solutions in hardware-constrained environments.
KEYWORDS:
Retinex algorithm, low-light image enhancement (LLIE), edge-preserving filter, FPGA implementation.
NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.
Block Diagram
Specifications
Software Requirements:
· Xilinx Vivado2018.3/Xilinx ISE Tool.
· HDL: Verilog.
Hardware Requirements:
· Microsoft® Windows XP.
· Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support.
· 512 MB RAM.
· 100 MB of available disk space.
Learning Outcomes
- Basics of Digital Electronics.
- Concept of encryption and decryption algorithm scheme
- Knowledge on reversible gates
- Introduction to Verilog Coding.
- Different modeling styles in Verilog.
o Data Flow modeling.
o Structural modeling.
o Behavioral modeling.
o Mixed level modeling.
- About cryptography.
- Knowledge on composite field.
- Applications in real time.
· Xilinx Vivado 2018.3/Xilinx ISE 14.7 Suite for design and simulation.
· Generation of Net list.
· Solution providing for real time problems.
· Project Development Skills:
o Problem Analysis Skills.
o Problem Solving Skills.
o Logical Skills.
o Designing Skills.
o Testing Skills.
o Debugging Skills.
o Presentation Skills.
o Thesis Writing Skills.
Paper Publishing
Request Call Back
Would you like to receive a free callback now?
Choose the best time for callback:
Leave your message and we will contact you as soon as possible
6-2-85/B, Old Maternity Hospital Road, Thyagaraja Nagar, Tirupati, Andhra Pradesh – 517501
+91 9030333433
+91 9393939065
0877-2261612
Disclaimer - Takeoff Edu Group Projects are not associated or affiliated with IEEE in any way. The IEEE Projects mentioned here are mentioned in the context of student projects, whose ideas are derived from IEEE publications, not projects of or by IEEE.
