A Low-Cost Error-Tolerant Flip-Flop Against SET and SEU for Dependable Designs

Also Available Domains Transistor Logic

Project Code :TVMABE439

Objective

The objective of “A Low?Cost Error?Tolerant Flip?Flop Against SET and SEU for Dependable Designs” is to propose a flip?flop circuit that is robust against soft errors—specifically single?event transients (SETs) and single?event upsets (SEUs)—while keeping area, power, and performance overheads low, making it suitable for dependable digital designs that require high reliability under radiation or transient fault conditions.

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Related Topics
  • Cadence EDA
  • Finite State Machines
  • Arithmetic Core
  • DSP Core
  • Communications
  • Nano Technology
  • Testing
  • Nano Technology
  • Cadence EDA
  • Low Power VLSI
  • Core Memories
  • Transistor Logic
  • FPGA
  • H-Spice
  • Cadence EDA
  • QCA
  • Xilinx Vivado
  • Xilinx ISE
  • Tanner EDA
  • LT-Spice
  • Matlab Interfacing
  • LT-Spice

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