A Lightweight LFSR-Based Strong Physical Unclonable Function Design on FPGA

Also Available Domains Design for Testability|Cadence EDA|Xilinx Vivado|Xilinx ISE

Project Code :TVREFE19_58

Objective

A PUF is like a fingerprint for a particular physical object, it is based on many manufacturing mismatches that occur during IC fabrication or the propagation delays that are present in the wires and interconnects.

Abstract

A PUF is like a fingerprint for a particular physical object, it is based on many manufacturing mismatches that occur during IC fabrication or the propagation delays that are present in the wires and interconnects. Physical unclonable function (PUF), a reliable physical security primitive, can be implemented in FPGAs and ASICs. Strong PUF is an important PUF classification that provides a large ‘‘Challenge Response’’ pairs (CRP) space for device authentication. However, most of the traditional strong PUF designs represented by the arbiter PUF are difficult to implement on FPGA. We propose a new lightweight strong PUF design that can dynamically reconfigure while maintaining high entropy and large CRP space.

NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.

Block Diagram

Specifications

Software Requirements:

·         Xilinx ISE 14.7

·         HDL: Verilog

Hardware Requirements:

·         Microsoft® Windows XP,

·         Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support

·         512 MB RAM

·         100 MB of available disk space

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