A Lightweight LFSR-Based Strong Physical Unclonable Function Design on FPGA
Also Available Domains Arithmetic Core|Communications|Xilinx ISE
Abstract
A PUF is like a fingerprint for a particular physical object, it is based on many manufacturing mismatches that occur during IC fabrication or the propagation delays that are present in the wires and interconnects. Physical unclonable function (PUF), a reliable physical security primitive, can be implemented in FPGAs and ASICs. Strong PUF is an important PUF classification that provides a large ‘‘Challenge Response’’ pairs (CRP) space for device authentication. However, most of the traditional strong PUF designs represented by the arbiter PUF are difficult to implement on FPGA. We propose a new lightweight strong PUF design that can dynamically reconfigure while maintaining high entropy and large CRP space.
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Block Diagram
Specifications
Software Requirements:
· Xilinx Vivado
· HDL: Verilog
Hardware Requirements:
· Microsoft® Windows XP,
· Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support
· 512 MB RAM
· 100 MB of available disk space
Learning Outcomes
- Basics of Digital Electronics
- FPGA design Flow
- Introduction to Verilog Coding
- Different modelling styles in Verilog
o Data Flow modeling
o Structural modeling
o Behavioral modeling
o Mixed level modeling
- Concept of LFSR
- Importance of security
- Drawbacks of existing methodologies
- Introduction to PUF
- Knowledge on PUF
- Knowledge on various types of PUF
- Applications of PUFin real time
- Scope of LFSR_PUF concept in today’s world
- Applications in real time
· Xilinx ISE 14.7/Xilinx Vivado for design and simulation
· Generation of Netlist
· Solution providing for real time problems
· Project Development Skills:
o Problem Analysis Skills
o Problem Solving Skills
o Logical Skills
o Designing Skills
o Testing Skills
o Debugging Skills
o Presentation Skills
o Thesis Writing Skills
Paper Publishing
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