A High-Speed, Low-Power, High-Reliability and Fully Single Event Double Node Upset Tolerant Design for Magnetic Random Access Memory

This project presents a high-speed, low-power, and high-reliability design for Magnetic Random Access Memory (MRAM) that is fully tolerant to Single Event Double Node Upsets (SEDNUs). MRAM, being a promising non-volatile memory technology, faces critical challenges when deployed in radiation-prone environments such as aerospace and defense applications. The proposed design incorporates novel fault-tolerant circuit techniques and robust cell architectures to mitigate the impact of radiation-induced upsets while maintaining high performance and energy efficiency. By integrating redundancy, error-resilient storage mechanisms, and optimized peripheral circuitry, the design ensures reliable data retention and access speed under adverse conditions. Implemented in a nanoscale CMOS process, the design achieves significant improvements in both operational speed and power consumption compared to conventional MRAM architectures. Simulation results demonstrate that the proposed approach effectively suppresses single event double node failures, thereby enhancing the resilience and longevity of MRAM devices. This work contributes toward the development of next-generation memory systems that can operate reliably in mission-critical and radiation-intensive applications.