Also Available Domains Xilinx Vivado|Xilinx ISE
The main objective of this project is to design a floating point multiply accumulator which comprises of signed soft multiplier and a single floating point accumulator.
In this article, a novel high-speed floating-point multiply-accumulator (FPMAC) is proposed. It comprises a signed soft multiplier and a single-cycle floating-point accumulator (FAAC). The multiplier is realized by a radix-4 Booth encoding based on sign-magnitude inputs. The FAAC contains a bidirectional shift alignment, a fast 3:1 compressor, and a three-operand leading-zero predictor (LZP). Due to the simplification of implementation steps, a short critical path, and a full-pipelined structure, our FPMAC achieves a high running speed while sustaining the good performance of delay and resource consumption.
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Specifications:
Software Requirements:
· Xilinx ISE14.7 Suite/Vivado2018.3 Tool.
· HDL: Verilog.
Hardware Requirements:
· Microsoft® Windows XP.
· Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support.
· 512 MB RAM.
· 100 MB of available disk space.
Learning Outcomes:
o Data Flow modeling.
o Structural modeling.
o Behavioral modeling.
o Mixed level modeling.