A High Performance Scan Flip-flop Design for Serial and Mixed Mode Scan Test

Over the years, serial scan design has become the de-facto design for testability technique. The ease of testing and high test coverage has made it gain widespread industrial acceptance. However, there are penalties associated with the serial scan design. These penalties include performance degradation, test data volume, test application time, and test power dissipation. The performance overhead of scan design is due to the scan multiplexers added to the inputs of every flip-flop. In today's very high-speed designs with minimum possible combinational depth, the performance degradation caused by the scan multiplexer has become magnified. Hence, to maintain circuit performance, the timing overhead of scan design must be addressed. In this paper, we propose a new scan flip-flop design that eliminates the performance overhead of serial scan. The proposed design removes the scan multiplexer from the functional path. The proposed design can help improve the functional frequency of performance critical designs. Furthermore, the proposed design can be used as a common scan flip-flop in the “mixed scan” test wherein it can be used as a serial scan cell as well as a random access scan (RAS) cell. The mixed scan test architecture has been implemented using the proposed scan flip-flop. The experimental results show a promising reduction in interconnect wire length, test time, and test data volume, compared to the state-of-the-art RAS and multiple serial scan implementations.