A High-Performance Multiply-Accumulate Unit by Integrating Additions and Accumulations into Partial Product Reduction Process
Also Available Domains Xilinx Vivado|Xilinx ISE
Objective
The main objective of this project is to implement a MAC architecture with Low power & reduced delay. The MAC unit was designed with mainly partial product generation and Accumulation units. Hence the delay can be reduced by integrating a part of additions into the partial product reduction (PPR) process
Abstract
In this project, we propose a low-power high-speed pipelined MAC architecture. Carry propagation of additions consume more power and large path-delay, to resolve this problem we introduce a proposed method. In this we integrate a part of additions into a partial product reduction process. Until the PPR process of next multiplication, addition and accumulation of MSB bits are not performed.
To correctly contrast with surplus in the PPR process, a small size adder is designed to accumulate the total number of carries. Resemble with traditional methods proposed method significantly reduce the power consumption and circuit area. The effectiveness of the proposed method is designed using Xilinx ISE 14.7/Xilinx Vivado software.
Keywords: Digital Circuits, Logic Circuits, Multiplying Circuits, Dadda multiplier.
NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.
Block Diagram
Specifications
Software Requirements:
- Xilinx ISE Tool/Xilinx Vivado
- HDL: Verilog
Hardware Requirements:
- Microsoft® Windows XP
- Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support
- 512 MB RAM
- 100 MB of available disk space
Learning Outcomes
- Basics of Digital Electronics
- FPGA design Flow
- Introduction to Verilog Coding
- Different modeling styles in Verilog
- Data Flow modeling
- Structural modeling
- Behavioral modeling
- Mixed level modeling
- Introduction to MAC unit
- About Partial Product Generation
- Partial Product Reduction method for both signed and unsigned numbers
- Knowledge on Adders
- About Registers
- Applications in real time
- Xilinx ISE 14.7/Xilinx Vivado for design and simulation
- Generation of Netlist
- Solution providing for real time problems
- Project Development Skills:
- Problem Analysis Skills
- Problem Solving Skills
- Logical Skills
- Designing Skills
- Testing Skills
- Debugging Skills
- Presentation Skills
- Thesis Writing Skills
Demo Video
Request for Video
Paper PublishingRequest Call Back
Would you like to receive a free callback now?
Choose the best time for callback:
Leave your message and we will contact you as soon as possible
6-2-85/B, Old Maternity Hospital Road, Thyagaraja Nagar, Tirupati, Andhra Pradesh – 517501
+91 9030333433
+91 9393939065
0877-2261612
Disclaimer - Takeoff Edu Group Projects are not associated or affiliated with IEEE in any way. The IEEE Projects mentioned here are mentioned in the context of student projects, whose ideas are derived from IEEE publications, not projects of or by IEEE.
