A Fully Digital Front-End Architecture for ECG Acquisition System with 0.5 V Supply

Also Available Domains Transistor Logic|Tanner EDA

Project Code :TVMATO217

Abstract

In this paper a new power-efficient electrocardiogram acquisition system is proposed. It uses a fully digital architecture to reduce the power consumption and chip area. The proposed architecture is compatible with digital CMOS technology and is capable of operating with a low supply voltage of 0.5 V. In this architecture, no analog block, e.g., low-noise amplifier (LNA), and filters, and no passive elements, such as ac coupling capacitors, are used. A moving average voltage-to time converter is used, which behaves instead of the LNA and antialiasing filter. A digital feedback loop is employed to cancel the impact of the dc offset on the circuit, which eliminates the need for coupling capacitors. The circuit is implemented in Cadence employing gpdk45nm CMOS technology.

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Block Diagram

Specifications

Software Requirements:

· Cadence Virtuoso

· Technology files: GPDK 45nm

Hardware Requirements:

· Microsoft® Windows XP

· Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support

· 512 MB RAM

· 100 MB of available disk space

Learning Outcomes

Introduction to Digital electronics
Introduction to Analog Circuits.

Knowledge on Voltage to time converter
Applications of VTC
Knowledge on the concept of filters
Applications of Counters and Demultiplexer

Importance of Transistors

MOS Fundamentals
NMOS/PMOS/CMOS Technologies
How to design circuits using Transistor logic?
Transistor level design for VTC
How to design Proposed circuits of control logic, counters and demultiplexers
Introduction to ECG acquisition system
Importance of offset cancellation
Scope of fully digital architecture in today’s world
Applications in Real time.

Cadence Virtuoso tool for design and simulation
Solution providing for real time problems

Project Development Skills:

Problem Analysis Skills
Problem Solving Skills
Logical Skills
Designing Skills
Testing Skills
Debugging Skills
Presentation skills
Thesis Writing Skills

Demo Video

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Front End Domains

Cadence EDA
Finite State Machines
Arithmetic Core
DSP Core
Communications
Nano Technology
Testing

Back End Domains

Nano Technology
Cadence EDA
Low Power VLSI
Core Memories
Transistor Logic

Tools

FPGA
H-Spice
Cadence EDA
QCA
Xilinx Vivado
Xilinx ISE
Tanner EDA
LT-Spice

Others

Matlab Interfacing

H-Spice

LT-Spice