A Fast Transient Response and High PSR Low Drop-Out Voltage Regulator
Also Available Domains Transistor Logic|Tanner EDA|Cadence EDA
Abstract
In this paper a low drop out regulator circuit proposed. It uses a fully analog architecture to reduce the power. The proposed architecture is compatible with analog CMOS technology and is capable of operating with a low supply voltage of 1.1 V. In this architecture, A low-dropout regulator (LDO), low-impedance transient-current enhanced (LTE) buffer, recycling-folded-cascode (RFC) are used to design a 1V low drop out regulator circuit The circuit is implemented in Cadence employing gpdk45nm CMOS technology
Keywords: low-dropout regulator (LDO), low-impedance transient-current enhanced (LTE) buffer, recycling-folded-cascode (RFC)
NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.
Demo Video
Request for Video
Paper PublishingRequest Call Back
Would you like to receive a free callback now?
Choose the best time for callback:
Leave your message and we will contact you as soon as possible
6-2-85/B, Old Maternity Hospital Road, Thyagaraja Nagar, Tirupati, Andhra Pradesh – 517501
+91 9030333433
+91 9393939065
0877-2261612
Disclaimer - Takeoff Edu Group Projects are not associated or affiliated with IEEE in any way. The IEEE Projects mentioned here are mentioned in the context of student projects, whose ideas are derived from IEEE publications, not projects of or by IEEE.
