A Fast Transient Response and High PSR Low Drop-Out Voltage Regulator
Also Available Domains Transistor Logic|Cadence EDA|LT-Spice
Abstract
In this paper a low drop out regulator circuit proposed. It uses a fully analog architecture to reduce the power. The proposed architecture is compatible with analog CMOS technology and is capable of operating with a low supply voltage of 1.1 V. In this architecture, A low-dropout regulator (LDO), low-impedance transient-current enhanced (LTE) buffer, recycling-folded-cascode (RFC) are used to design a 1V low drop out regulator circuit The circuit is implemented in Cadence employing gpdk45nm CMOS technology
Keywords: low-dropout regulator (LDO), low-impedance transient-current enhanced (LTE) buffer, recycling-folded-cascode (RFC)
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