A Fast Transient Response and High PSR Low Drop-Out Voltage Regulator

Also Available Domains Tanner EDA|Cadence EDA|LT-Spice

Project Code :TVMABE167

Abstract

In this project, a low drop-out (LDO) linear regulator with high power supply rejection ratio (PSR) and fast transient response is proposed for various applications. To achieve fast transient response, this work employs variable bias and transient boost capacitance. The variable bias structure enhance the slew rate and PSR of LDO. The transient-boost capacitance (TBC) is set in a proper location, using its voltage characteristic to enhance transient response without consuming quiescent current, and it also improves circuit's stability. This circuit is designed based on TSMC 90nm gpdk CMOS Technology and verified by Cadence simulation environment. According to the simulation results, the LDO achieves a better PSR at particular frequency range.

NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.

Block Diagram

Specifications

Software Requirements:

· Cadence virtuoso

· Technology files: 90 nm gpdk.

Hardware Requirements:

· Microsoft® Windows XP

· Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support

· 512 MB RAM

· 100 MB of available disk space

Learning Outcomes

· Introduction to Analog & Digital Electronics

· Basic concepts of Amplifier

o Different types of Amplifiers

o Advantages & Limitations of Amplifier

· Basics of LDO Concept.

· Learning of tool cadence virtuoso

· Transistor level design in Cadence Virtuoso

· Analysis of design and results

· Scope of LDO in today’s world

· Real time Applications.

Demo Video

Front End Domains

Cadence EDA
Finite State Machines
Arithmetic Core
DSP Core
Communications
Nano Technology
Testing

Back End Domains

Nano Technology
Cadence EDA
Low Power VLSI
Core Memories
Transistor Logic

Tools

FPGA
H-Spice
Cadence EDA
QCA
Xilinx Vivado
Xilinx ISE
Tanner EDA
LT-Spice

Others

Matlab Interfacing

H-Spice

LT-Spice