A Design of 45nm Low Jitter Charge Pump PhaseLocked Loop Architecture for VHF and UHF Field

Project Code :TVPGBE166

Objective

The primary goal is to construct a complete PLL that supports both analog and digital circuits, emphasizing its critical role in clock generation and recovery in microprocessors, communication systems, digital networking, and frequency synthesizers. PLLs are particularly important in high-performance digital systems for generating accurately timed on-chip clocks

Abstract

The Phase-locked loop (PLL) has played a crucial role in advancing technology within data transmission and communication sectors. Moreover, recent research integrating PLL schemes with innovative integrated circuit technologies has underscored the importance of PLL devices as integral system elements. This study developed a PLL device capable of handling an input voltage of 1.0 V, tested using the 45 nm NCSU PDK alongside Cadence Virtuoso tools. The goal was to achieve an output frequency exceeding 800 MHz and a low jitter of 150 ps. Additionally, the methodology employed the Ocean language to examine the fluctuations in PLL parameters such as output voltage, operational frequency, and phase jitter.

NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.

Block Diagram

Specifications

Specifications:

Software Requirements:

Tool: Cadence Virtuoso
Technology: GPDK 45nm

Hardware Requirements:

Microsoft® Windows XP
Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support
512 MB RAM
100 MB of available disk space

Learning Outcomes

Learning Outcomes:

· Introduction to Analog & Digital Electronics

· Necessity of PLL.

· Advantages & Applications of PLL.

· Basics of VCO

o Different configurations of VCO

· Knowledge on Low pass filter

· Design of PLL in Cadence

· Analysis of simulation results & Outputs

· Scope of PLL in today’s world.

· Real time applications of PLL.

Demo Video

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Front End Domains

DSP Core
Communications and Crypto Core
Design for Testability
Arithmetic Core
Nano Technology

Back End Domains

Nano Technology
Core Memories
Transistor Logic
Low Power VLSI

Tools

Cadence EDA
Xilinx Vivado
Xilinx ISE
Tanner EDA
FPGA

Others

Matlab Interfacing