A DC to 20 GHz Variable Gain Amplifier with Tunable Input Matching in 22 nm FDSOI Technology

Error correction codes (ECCs) are commonly used to look after memories next to errors. The proposed technique we are detect the one or more errors and to correct on its own bit error. Among ECCs, Orthogonal Latin Squares (OLS) codes have gain renewed interest for memory defense due to their modularity and the simplicity of the decoding algorithm that enable low down delay implementations. The general idea for achieving error detection and correction is to add some redundancy which means to add some extra data to a message, which receiver can use to check uniformity of the delivered message, and to pick up data determined to be corrupt. A significant issue is that when ECCs is used, the encoder and decoder circuits can also suffer errors. In this brief, a concurrent error detection technique designed for OLS codes encoders be proposed and evaluated. The proposed method uses the properties of OLS codes in the direction of efficiently implement a parity prediction scheme that protects the encoder.