A Coupled Variable Input LCG Method and its VLSI Architecture for Pseudorandom Bit Generation

Also Available Domains Arithmetic Core|Xilinx Vivado

Project Code :TVMATO661

Objective

The main objective of the LCG is to generate a random output based on the constant inputs and seed inputs. It produces a valid output for certain combinations thereby effects the possibility of maximum sequence length

Abstract

In this project, a new efficient PRBG method, i.e., “coupled variable input LCG (CVLCG)” and its architecture are proposed. The dual coupled-LCG (dual-CLCG) is a secure pseudorandom bit generator (PRBG) method amongst various LFSR, LCG and chaotic based PRBG methods for generating a pseudorandom bit sequence. The hardware implementation of this method has a bottleneck due to the involvement of inequality equations. Initially, a direct architectural mapping of the dual CLCG method is performed. Since two inequality equations are involved for coupling, it generates pseudorandom bit at unequal interval of time that leads to large variation in output latency. Besides, it consumes a large area and fails to achieve the maximal period. Hence, to overcome the aforesaid drawbacks coupled variable input LCG (CVLCG) is proposed. The novelty of the proposed method is the coupling of two newly formed variable input LCGs that generates pseudorandom bit at every uniform clock rate, attains maximum length sequence and reduces one comparator area as compared to the dual-CLCG architecture.

NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.

Block Diagram

Specifications

Software Requirements:

Xilinx ISE tool
HDL: Verilog

Hardware Requirements:

Microsoft® Windows XP
Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support
512 MB RAM
100 MB of available disk space

Learning Outcomes

Basics of Digital Electronics
VLSI design Flow
Introduction to Verilog Coding
Different modeling styles in Verilog

Data Flow modeling
Structural modeling
Behavioral modeling
Mixed level modeling

Introduction to cryptography
About pseudo random bit generators
Knowledge on LCG PRBG
Different hardware related PRBG algorithms
Knowledge on architectural designs of LCG, CLCG,DCLCG etc
Applications in real time
Xilinx ISE 14.7 for design and simulation
Generation of Netlist
Solution providing for real time problems
Project Development Skills:

Problem Analysis Skills
Problem Solving Skills
Logical Skills
Designing Skills
Testing Skills
Debugging Skills
Presentation Skills
Thesis Writing Skills

Demo Video

Front End Domains

Cadence EDA
Finite State Machines
Arithmetic Core
DSP Core
Communications
Nano Technology
Testing

Back End Domains

Nano Technology
Cadence EDA
Low Power VLSI
Core Memories
Transistor Logic

Tools

FPGA
H-Spice
Cadence EDA
QCA
Xilinx Vivado
Xilinx ISE
Tanner EDA
LT-Spice

Others

Matlab Interfacing

H-Spice

LT-Spice