A Combined SDC-SDF Architecture for Normal IO Pipelined Radix-2 FFT
Also Available Domains DSP Core|Xilinx Vivado
Abstract
We present an efficient combined single-path delay commutator-feedback (SDC-SDF) radix-2 pipelined fast Fourier transform architecture, which includes log2 N − 1 SDC stages, and 1 SDF stage. The SDC processing engine is proposed to achieve 100% hardware resource utilization by sharing the common arithmetic resource in the time-multiplexed approach, including both adders and multipliers. Thus, the required number of complex multipliers is reduced to log4 N − 0.5, compared with log2 N − 1 for the other radix-2 SDC/SDF architectures. In addition, the proposed architecture requires roughly minimum number of complex adders log2 N + 1 and complex delay memory 2N + 1.5 log2 N − 1.5.
Index Terms—Fast Fourier transforms (FFT), pipelined architecture, single-path delay communicator processing engine (SDC PE).
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Specifications
Hardware requirement
Processor - Pentium –III
Speed - 1.1 GHz
RAM - 1 GB (min)
Hard Disk - 40 GB
Floppy Drive - 1.44 MB
Key Board - Standard Windows Keyboard
Mouse - Two or Three Button Mouse
Monitor - SVGA
Software requirements
v Operating System :Windows95/98/2000/XP/Windows7
v Front End : Modelsim 6.3 for Debugging and Xilinx 14.3 for Synthesis and Hard Ware Implementation
v This software’s where Verilog source code can be used for design implementation.
Learning Outcomes
- Basics of Digital Electronics
- VLSI design Flow
- Introduction Radix-2 FFT
- Writing Verilog code.
- Introduction to SDC-SDF architecture.
- Knowledge on pipelined concept.
- Applications in real time
· Xilinx tool for writing code, synthesis and simulation
· Solution providing for real time problems
· Project Development Skills:
o Problem Analysis Skills
o Problem Solving Skills
o Logical Skills
o Designing Skills
o Testing Skills
o Debugging Skills
o Presentation Skills
o Thesis Writing Skills
Paper Publishing
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