A Circuit Technique for Leakage Power reduction in CMOS VLSI Circuits

Abstract:

This paper presents a circuit technique aimed at reducing leakage power in CMOS VLSI circuits. With the advancement of CMOS technology, leakage currents have become a significant concern, especially in the ultra-deep-submicron region. Minimizing leakage currents is crucial to ensure proper circuit operation. Designing nanoscale CMOS circuits that are free from leakage poses a formidable challenge. In this study, we propose a circuit technique that effectively controls the voltage at the source terminal of MOSFETs to mitigate leakage currents. By employing this technique, we observe a significant improvement in static power dissipation and overall power consumption in the designed CMOS inverter compared to conventional designs. Furthermore, simulation results demonstrate enhanced power efficiency in NAND and NOR gates implemented using the same approach, as well as in an 11-stage CMOS ring oscillator.  A comparison with existing techniques considering power dissipation and delay is also provided, highlighting the favorable Power-Delay Product (PDP) achieved by the proposed circuits. The findings of this study indicate the potential of the proposed technique for reducing leakage power and improving power efficiency in CMOS VLSI circuits.