A 7t Security Oriented SRAM Bitcell

Also Available Domains Cadence EDA|Transistor Logic|Tanner EDA

Project Code :TVMATO644

Objective

The main aim of this project is to provide the security to data by using some additional transistor to SRAM cell. The leakage power is also reduced by using this design

Abstract

In this project, a security-oriented 7T SRAM cell is proposed to provide resiliency of the power analysis attacks, which incorporates an additional transistor to the original 6T SRAM implementation and a two-phase write operation, which significantly reduces the correlation between the stored data and the power consumption during write operations.Power analysis (PA) of current consumed by the power supply of the system have become a serious threat to any security systems by enabling secret data extraction through the analysis. Embedded memories, called Static Random Access Memory (SRAM) cells often implemented with six-transistor (6T), serves as a key component in many of these systems. However, the conventional SRAM cells are prone to side-channel power analysis attacks due to the correlation between their current characteristics and written data.

NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.

Block Diagram

Specifications

Software Requirements:

Cadence EDA
Technology files:180nm

Hardware Requirements:

Microsoft® Windows XP
Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support
512 MB RAM
100 MB of available disk space

Learning Outcomes

Introduction Core memories
Transistors & its applications

Types of Transistors
Logic Gates using Transistors
Pull Up and Pull Down networks
Importance of Transistors

MOS Fundamentals
NMOS/PMOS/CMOS Technologies
How to design circuits using Transistor logic?
Transistor level design for core memories
How to design low power, high speed area efficient transistor level circuits?
Drawbacks in CMOS technology
Scope of memories in today’s world
Applications in real time
Cadence EDA tool for design and simulation
Solution providing for real time problems
Project Development Skills:

Problem Analysis Skills
Problem Solving Skills
Logical Skills
Designing Skills
Testing Skills
Debugging Skills
Presentation skills
Thesis Writing Skills

Demo Video

Front End Domains

Cadence EDA
Finite State Machines
Arithmetic Core
DSP Core
Communications
Nano Technology
Testing

Back End Domains

Nano Technology
Cadence EDA
Low Power VLSI
Core Memories
Transistor Logic

Tools

FPGA
H-Spice
Cadence EDA
QCA
Xilinx Vivado
Xilinx ISE
Tanner EDA
LT-Spice

Others

Matlab Interfacing

H-Spice

LT-Spice