A 521pW, 0.016 V Line Sensitivity Self-Biased CMOS Voltage Reference With DIBL Effect Compensation Using Adaptive VGS Control

This proposal presents an ultra-low-power self-biased CMOS voltage reference (SBCVR) that incorporates drain-induced-barrier-lowering (DIBL) effect compensation to enhance line sensitivity (LS) and low-frequency power supply rejection ratio (PSRR). To minimize the bias current (IB) dependence on the supply voltage (VDD) due to the DIBL effect, the gate-source voltage (VGS) of the biasing transistor is dynamically adjusted in response to VDD. This approach ensures compensation for the DIBL effect while maintaining IB's stability against variations in VDD. The SBCVR is implemented in a 0.18-μm CMOS process, and 18 samples were tested. The results demonstrate an average LS of 0.016%/V, which is approximately 85% lower than the version without DIBL compensation. The design also achieves a PSRR of −62.5dB at 10Hz. additionally, the average reference voltage (VREF) is 317.6mV, with a variation of 0.52% (σ/μ). The average temperature coefficient (TC) is 86.6 ppm/°Cover the range of 0°C to 100°C without trimming, and the minimum power consumption at 27°C is 521pW. The SBCVR, with DIBL compensation, occupies only 0.0016mm².

Key words:- —CMOS voltage reference, DIBL effect compensation, line sensitivity, power supply rejection ratio, self-biased, ultra-low power