A 4-read 2-write multi-port register file design using pulsed latches
Also Available Domains Low Power VLSI
Objective
The main aim of this work is to implement the multiport register file using pulse based latches.By using Latch based registers the power will be reduced.
Abstract
In this project, an area efficient and low power consumption design approach is proposed to perform the multi-read and multi-write operations in the pulsed-latches based multiport register files. These register files showed significant decrease in area as well as power consumption when compared to the SRAM based register files. An 8-BIT 4-READ and 2-WRITE (4R2W) pulsed-latches based multiport register file were designed and simulated in 180nm technology and its power-delay product was analyzed.
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Block Diagram
Specifications
Software Requirements:
- Tanner EDA
- Technology files:180nm
Hardware Requirements:
- Microsoft® Windows XP
- Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support
- 512 MB RAM
- 100 MB of available disk space
Learning Outcomes
- Introduction Core memories
- Transistors & its applications
- Types of Transistors
- Logic Gates using Transistors
- Pull Up and Pull Down networks
- Importance of Transistors
- MOS Fundamentals
- NMOS/PMOS/CMOS Technologies
- How to design circuits using Transistor logic?
- Transistor level design for core memories
- How to design low power, high speed area efficient transistor level circuits?
- Drawbacks in CMOS technology
- Scope of memories in today’s world
- Applications in real time
- Tanner EDA tool for design and simulation
- Solution providing for real time problems
- Project Development Skills:
- Problem Analysis Skills
- Logical Skills
- Designing Skills
- Testing Skills
- Debugging Skills
- Presentation skills
- Thesis Writing Skills
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