A 32-Bit Ripple-Ling Hybrid Carry Adder
Also Available Domains DSP Core
Objective
To design and implement a high-performance adder that combines the efficiency of ripple carry and carry look-ahead techniques to optimize speed and power consumption. The hybrid approach aims to reduce propagation delay while maintaining simplicity and scalability.
Abstract
This paper presents a hybrid carry adder design that combines high-order Ling-based parallel prefix techniques with low-order ripple-carry structures to optimize performance and simplicity. The low 11 bits are computed using a ripple-carry approach, reducing complexity, while the high 21 bits leverage a Ling-based structure to maintain a short critical path. By introducing novel intermediate variables and leveraging Shannon expansion, the design achieves efficient computation of the output sum with minimal delay in the control signal of the output multiplexer. Additionally, the output sum circuit is custom-designed using reusable logic circuits, further enhancing the efficiency and scalability of the proposed adder architecture.
Keywords— Adder, ripple carry, Ling carry, low power, low cost.
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Block Diagram
Specifications
Software Requirements:
VIVADO 2018.3
Hardware Requirements:
· Microsoft® Windows XP
· Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support
· 512 MB RAM
· 100 MB of available disk space
Learning Outcomes
- Basics of Digital Electronics
- VLSI design Flow
- Applications in real time
· VIVADO for design and simulation
· Solution providing for real time problems
· Project Development Skills:
o Problem Analysis Skills
o Problem Solving Skills
o Logical Skills
o Designing Skills
o Testing Skills
o Debugging Skills
o Presentation Skills
o Thesis Writing Skills
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