A 300-mV Auto Shutdown Comparator-Based Continuous Time Modulator

Also Available Domains Low Power VLSI|Tanner EDA|Cadence EDA

Project Code :TVPGBE75

Objective

The main aim of this work is to reduce the power for auto-shutdown comparator and it is implemented with a fully passive loop filter based CTDSM in standard 180-nm CMOS mixed-mode process. Through this method, the power can be reduced.

Abstract

In this project, a 300-mV, auto shutdown comparator is proposed by using a novel clock gating network. The proposed auto shutdown comparator is further employed to realize a compact, ultralow power Continuous Time Delta Sigma Modulator (CTDSM) with a 300-mV supply voltage for multichannel sensing and biomedical applications.

The design is implemented using 180-nmtechnology. With the clock-gated auto shutdown comparator, the CTDSM consumes a less core power thereby providing more power saving. The proposed design is implemented using 180nm technology in Cadence Virtuoso.

Keywords: Analog-to-digital converter (ADC), Comparator, Continuous Time Delta Sigma Modulator (CTDSM).

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