A 21-Transistor Single-Phase-Clocked Flip-Flop With Low Leakage Current for Near-Threshold Voltage Operation

Project Code :TVMABE794

Objective

This work presents the design and implementation of a 21-transistor (21T) single-phase-clocked flip-flop optimized for low leakage current operation under near-threshold voltage conditions. As modern digital systems increasingly demand ultra-low power consumption for portable and energy-constrained applications, operating circuits at near-threshold voltages has become an effective strategy

Abstract

The proposed flip-flop utilizes a single-phase clocking scheme to simplify clock distribution and reduce dynamic power consumption. The 21T architecture is carefully designed to minimize leakage paths while maintaining robust data retention and switching performance. Techniques such as transistor stacking, optimized sizing, and efficient feedback mechanisms are employed to enhance stability and reduce power dissipation.

The design is implemented using CMOS technology and evaluated in terms of power consumption, leakage current, delay, and power-delay product (PDP). Simulation results demonstrate that the proposed flip-flop achieves significantly reduced leakage current and improved energy efficiency while maintaining reliable operation at near-threshold voltages, making it suitable for low-power VLSI systems.

Keywords

Flip-Flop, Single-Phase Clocking, Low Leakage, Near-Threshold Voltage, CMOS, Low Power, VLSI Design

NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.

Block Diagram

Specifications

· Tool Used: Cadence EDA tools for schematic and simulation

· Technology Node:180nm CMOS process.

· Design Elements: complementary compound push–pull pair (PMOS + NMOS), input matching network, L1 & L2 (0.5 pH–10 pH) inductors, high-value output load (RL, 100 kΩ–1 MΩ), biasing/level-shift network, feedback/compensation path, input/output coupling and decoupling capacitors, thermal-stabilization circuitry, and symmetric/layout considerations for reduced mismatch

· Optimization Goal: minimize circuit complexity and parasitics (transistor and passive count) while preserving ultra-wideband large-signal gain, low output noise, high temperature stability, and linearity across the desired cutoff range (e.g., maintain cutoff from ≈18.21 kHz up to hundreds of GHz in simulation) with low power consumption (~69 mW)v

Learning Outcomes

Understanding of Flip-Flop Design

• Knowledge of Low-Power Design Techniques

• Application of Near-Threshold Computing

• Leakage Reduction Methods (Transistor Stacking)

• Performance Analysis Using PDP

• Experience with CMOS Circuit Simulation

Demo Video

Request Video

Front End Domains

Cadence EDA
Finite State Machines
Arithmetic Core
DSP Core
Communications
Nano Technology
Testing

Back End Domains

Nano Technology
Cadence EDA
Low Power VLSI
Core Memories
Transistor Logic

Tools

FPGA
H-Spice
Cadence EDA
QCA
Xilinx Vivado
Xilinx ISE
Tanner EDA
LT-Spice

Others

Matlab Interfacing

H-Spice

LT-Spice