8-Bit ALU Design using m-GDI Technique
Also Available Domains Transistor Logic|Cadence EDA
Objective
The main objective of this project is to reduce the power consumption and delay by using GDI technique for implementing the ALU circuit.
Abstract
In this project, an 8-bit Arithmetic Logic Unit (ALU) using Gate Diffusion Input (GDI) technique is proposed. Implementing the GDI technique in designing the ALU requires less number of transistors which result in reduced chip-area and power consumption – two of the most important parameters in digital VLSI design. In this design, 3T XOR is used in the full adder. Moreover, a novel 1-to-8 de multiplexer circuit has been used in the design as well. By using this method, we can reduce the power consumption in ALU design
NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.
Block Diagram
Specifications
Software Requirements:
- Tanner EDA
- Technology files: 180nm
Hardware Requirements:
- Microsoft® Windows XP
- Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support
- 512 MB RAM
- 100 MB of available disk space
Learning Outcomes
- Introduction Core memories
- Transistors & its applications
- Types of Transistors
- Logic Gates using Transistors
- Pull Up and Pull Down networks
- Importance of Transistors
- MOS Fundamentals
- NMOS/PMOS/CMOS Technologies
- How to design circuits using Transistor logic?
- Transistor level design for core memories
- How to design low power, high speed area efficient transistor level circuits?
- Drawbacks in CMOS technology
- Scope of memories in today’s world
- Applications in real time
- Tanner EDA tool for design and simulation
- Solution providing for real time problems
- Project Development Skills:
- Problem Analysis Skills
- Problem Solving Skills
- Logical Skills
- Designing Skills
- Testing Skills
- Debugging Skills
- Presentation skills
- Thesis Writing Skills
Paper Publishing
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