7T Security-Oriented SRAM Bit cell

The objective of this work is to design and analyze a 7T security-oriented SRAM bit cell that enhances data confidentiality and robustness against hardware security threats such as read disturb, data remanence, side-channel leakage, and fault-based attacks. The proposed design aims to improve read stability, write reliability, and noise margins while incorporating intrinsic security features such as controlled read access, reduced information leakage, and improved resistance to invasive and non-invasive attacks, all with minimal overhead in area, power, and delay. The bit cell is evaluated through detailed simulations and layout-aware analysis to demonstrate its suitability for secure embedded memories in IoT, cryptographic processors, and trusted SoC applications.