32-bit RISC-V Processor with Switchable Floating Point ALU

This project presents the design and implementation of a 32-bit RISC-V processor featuring a switchable Floating-Point Arithmetic Logic Unit (FP-ALU) for enhanced computational flexibility. The processor is based on the RV32I instruction set architecture and supports both integer and floating-point operations through a configurable execution pipeline. The switchable FP-ALU allows dynamic selection between integer ALU mode and IEEE-754–compliant floating-point mode, enabling efficient execution of arithmetic-intensive applications without compromising hardware simplicity. The architecture includes optimized modules for instruction fetch, decode, register file, ALU, FP-ALU, control unit, and pipeline hazard management. The processor is described in Verilog HDL and synthesized on an FPGA to evaluate performance, area, and power. Experimental results demonstrate significant improvements in throughput for floating-point workloads while maintaining low resource utilization. The proposed design provides a balanced trade-off between performance and hardware cost, making it suitable for embedded, IoT, and signal-processing applications requiring mixed-precision computation. To maintain smooth pipeline flow, techniques like hazard detection, stalling, and forwarding are used to minimize delays. The complete design is written in Verilog HDL and synthesized, simulated, and tested using the Vivado design suite on FPGA hardware.

Keywords: - RISC-V Processor, 5-Stage Pipeline, Verilog HDL, Vivado, integer ALU, floating-point ALU, FPGA Implementation.