32-Bit Mac Unit Using Vedic Multiplier and Carry Save Adder

Also Available Domains Arithmetic Core|Xilinx Vivado

Project Code :TVMATO677

Objective

The main objective of this paper is to implement the high performance 32-bit MAC unit. The MAC unit is designed with Vedic multiplier structure with reduced delay

Abstract

In this project The Multiply-Accumulate Unit (MAC) is an integral computational component of all Digital Signal Processing (DSP) architectures and thus has a significant impact on their speed and power dissipation and area overhead. To reduce the delay and area consumption the adders and multipliers are replaced with efficient adder and multiplier thereby implementing an efficient MAC unit. In this paper, an efficient and high performance MAC unit is implemented using carry save adder and Vedic multiplier for 32 bit operands. The proposed MAC unit has better area and delay compared to the existing MAC unit. 

NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.

Block Diagram

Specifications

Software Requirements:

  • Xilinx ISE 
  • VHDL

Hardware Requirements:

  • Microsoft® Windows XP
  • Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support 
  • 512 MB RAM
  • 100 MB of available disk space

Learning Outcomes

  • Basics of Digital Electronics
  • VLSI design Flow
  • Introduction to VHDL Coding
  • Introduction to Vivado tool
  • Knowledge on Adder circuits
  • About Vedic multiplier 
  • Different types of multipliers
  • Knowledge on Vedic multiplication and accumulation
  • About carry save adder
  • Applications of multipliers in real time
  • Xilinx ISE for design and simulation
  • Generation of Netlist
  • Solution providing for real time problems
  • Project Development Skills:
    • Problem Analysis Skills
    • Problem Solving Skills
    • Logical Skills
    • Designing Skills
    • Testing Skills
    • Debugging Skills
    • Presentation Skills
    • Thesis Writing Skills

Demo Video