2T XOR-Based Content Addressable Memory

Also Available Domains Core Memories|Cadence EDA|Tanner EDA

Project Code :TVMATO434

Objective

The main objective of this project is to design the CAM structure with high performance in terms of area, power, and speed. The CAM structure is designed with a novel 2T XOR method and it is used to replace the 4T XOR module to better perform

Abstract

In this project, a novel 2T XOR module is introduced to replace 4T XOR module in order to achieve high speed, low power consumption, low area in Parameter extractor. Parameter extractor is the main part of the CAM that consumes more power and it uses an array of XOR gates which leads to more power dissipation. Simulation results show that the 2T XOR module consumes less power and high speed when compared with 14T and4T XOR gates. The proposed design is implemented using 180nm technology in Cadence Virtuoso.

Keywords: Content Addressable Memory (CAM), 4T XOR, 2T XOR, Logic Gates.

NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.

Block Diagram

Specifications

Software Requirements:

Cadence Virtuoso
Technology files:180nm

Hardware Requirements:

Microsoft® Windows XP
Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support
512 MB RAM
100 MB of available disk space

Learning Outcomes

Introduction to Core memories
Transistors & its applications

Types of Transistors
Logic Gates using Transistors
Pull Up and Pull Down networks
Importance of Transistors

MOS Fundamentals
NMOS/PMOS/CMOS Technologies
How to design circuits using Transistor logic?
Transistor level design for core memories
How to design low power, high speed area efficient transistor level circuits?
Drawbacks in CMOS technology
Scope of memories in today’s world
Applications in real time
Cadence Virtuoso tool for design
Timing analysis
Power analysis
Solution providing for real time problems
Project Development Skills:

Problem Analysis Skills
Problem Solving Skills
Logical Skills
Designing Skills
Testing Skills
Debugging Skills
Presentation skills
Thesis Writing Skills

Demo Video

Front End Domains

Cadence EDA
Finite State Machines
Arithmetic Core
DSP Core
Communications
Nano Technology
Testing

Back End Domains

Nano Technology
Cadence EDA
Low Power VLSI
Core Memories
Transistor Logic

Tools

FPGA
H-Spice
Cadence EDA
QCA
Xilinx Vivado
Xilinx ISE
Tanner EDA
LT-Spice

Others

Matlab Interfacing

H-Spice

LT-Spice