S.no
Project Code
Project Name
Action
1 TVPGTO658 Virtex 7 FPGA Implementation of 256 Bit Key AES Algorithm with Key Sch...

Communications and Crypto Core|Xilinx Vivado|Xilinx ISE

2 TVPGTO659 MapReduce Model Using FPGA Acceleration for Chromosome Y Sequence Mapp...

DSP Core|Xilinx Vivado|Xilinx ISE

Items per page:
1 – 2 of 2
S.no
Project Code
Project Name
Action
1 TVPGTO658 Virtex 7 FPGA Implementation of 256 Bit Key AES Algorithm with Key Sch...

Communications and Crypto Core|Xilinx Vivado|Xilinx ISE

2 TVPGTO659 MapReduce Model Using FPGA Acceleration for Chromosome Y Sequence Mapp...

DSP Core|Xilinx Vivado|Xilinx ISE

Items per page:
1 – 2 of 2
S.no
Project Code
Project Name
Action
1 TVPGTO658 Virtex 7 FPGA Implementation of 256 Bit Key AES Algorithm with Key Sch...

Communications and Crypto Core|Xilinx Vivado|Xilinx ISE

2 TVPGTO659 MapReduce Model Using FPGA Acceleration for Chromosome Y Sequence Mapp...

DSP Core|Xilinx Vivado|Xilinx ISE

Items per page:
1 – 2 of 2
Final year projects