Project Code: TVPGTO658

Project Title:Virtex 7 FPGA Implementation of 256 Bit Key AES Algorithm with Key Schedule and Sub Bytes Block Optimization

Communications and Crypto Core| Xilinx Vivado| Xilinx ISE

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Project Code: TVPGTO659

Project Title:MapReduce Model Using FPGA Acceleration for Chromosome Y Sequence Mapping

DSP Core| Xilinx Vivado| Xilinx ISE

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Project Name
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1 TVPGTO658 Virtex 7 FPGA Implementation of 256 Bit Key AES Algorithm with Key Sch...

Communications and Crypto Core|Xilinx Vivado|Xilinx ISE

2 TVPGTO659 MapReduce Model Using FPGA Acceleration for Chromosome Y Sequence Mapp...

DSP Core|Xilinx Vivado|Xilinx ISE

Items per page:
1 – 2 of 2

Project Code: TVPGTO658

Project Title:Virtex 7 FPGA Implementation of 256 Bit Key AES Algorithm with Key Schedule and Sub Bytes Block Optimization

Communications and Crypto Core| Xilinx Vivado| Xilinx ISE

View Details

Project Code: TVPGTO659

Project Title:MapReduce Model Using FPGA Acceleration for Chromosome Y Sequence Mapping

DSP Core| Xilinx Vivado| Xilinx ISE

View Details
Items per page:
1 – 2 of 2
S.no
Project Code
Project Name
Action
1 TVPGTO658 Virtex 7 FPGA Implementation of 256 Bit Key AES Algorithm with Key Sch...

Communications and Crypto Core|Xilinx Vivado|Xilinx ISE

2 TVPGTO659 MapReduce Model Using FPGA Acceleration for Chromosome Y Sequence Mapp...

DSP Core|Xilinx Vivado|Xilinx ISE

Items per page:
1 – 2 of 2

Project Code: TVPGTO658

Project Title:Virtex 7 FPGA Implementation of 256 Bit Key AES Algorithm with Key Schedule and Sub Bytes Block Optimization

Communications and Crypto Core| Xilinx Vivado| Xilinx ISE

View Details

Project Code: TVPGTO659

Project Title:MapReduce Model Using FPGA Acceleration for Chromosome Y Sequence Mapping

DSP Core| Xilinx Vivado| Xilinx ISE

View Details
Items per page:
1 – 2 of 2
S.no
Project Code
Project Name
Action
1 TVPGTO658 Virtex 7 FPGA Implementation of 256 Bit Key AES Algorithm with Key Sch...

Communications and Crypto Core|Xilinx Vivado|Xilinx ISE

2 TVPGTO659 MapReduce Model Using FPGA Acceleration for Chromosome Y Sequence Mapp...

DSP Core|Xilinx Vivado|Xilinx ISE

Items per page:
1 – 2 of 2
Related Topics
  • Arithmetic Core
  • DSP Core
  • Communications and Crypto Core
  • Design for Testability
  • Nano Technology
  • Low Power VLSI
  • Transistor Logic
  • Core Memories
  • FPGA
  • Cadence EDA
  • Xilinx Vivado
  • Xilinx ISE
  • Tanner EDA
  • Matlab Interfacing
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