Project Code: TVPGTO658
Project Title:Virtex 7 FPGA Implementation of 256 Bit Key AES Algorithm with Key Schedule and Sub Bytes Block OptimizationCommunications and Crypto Core| Xilinx Vivado| Xilinx ISE
View DetailsProject Code: TVPGTO659
Project Title:MapReduce Model Using FPGA Acceleration for Chromosome Y Sequence MappingDSP Core| Xilinx Vivado| Xilinx ISE
View Details S.no | Project Code | Project Name | Action |
---|---|---|---|
1 | TVPGTO658 | Virtex 7 FPGA Implementation of 256 Bit Key AES Algorithm with Key Sch... | |
2 | TVPGTO659 | MapReduce Model Using FPGA Acceleration for Chromosome Y Sequence Mapp... |
Project Code: TVPGTO658
Project Title:Virtex 7 FPGA Implementation of 256 Bit Key AES Algorithm with Key Schedule and Sub Bytes Block OptimizationCommunications and Crypto Core| Xilinx Vivado| Xilinx ISE
View DetailsProject Code: TVPGTO659
Project Title:MapReduce Model Using FPGA Acceleration for Chromosome Y Sequence MappingDSP Core| Xilinx Vivado| Xilinx ISE
View Details S.no | Project Code | Project Name | Action |
---|---|---|---|
1 | TVPGTO658 | Virtex 7 FPGA Implementation of 256 Bit Key AES Algorithm with Key Sch... | |
2 | TVPGTO659 | MapReduce Model Using FPGA Acceleration for Chromosome Y Sequence Mapp... |
Project Code: TVPGTO658
Project Title:Virtex 7 FPGA Implementation of 256 Bit Key AES Algorithm with Key Schedule and Sub Bytes Block OptimizationCommunications and Crypto Core| Xilinx Vivado| Xilinx ISE
View DetailsProject Code: TVPGTO659
Project Title:MapReduce Model Using FPGA Acceleration for Chromosome Y Sequence MappingDSP Core| Xilinx Vivado| Xilinx ISE
View Details S.no | Project Code | Project Name | Action |
---|---|---|---|
1 | TVPGTO658 | Virtex 7 FPGA Implementation of 256 Bit Key AES Algorithm with Key Sch... | |
2 | TVPGTO659 | MapReduce Model Using FPGA Acceleration for Chromosome Y Sequence Mapp... |