Paper PublishingProject Code: TVPGBE124
Project Title:Novel Ternary Adder and Multiplier Designs Without Using Decoders or EncodersView DetailsProject Code: TVPGBE123
Project Title:Comparative Analysis of Memristor Models with a Window Function Described in LTspiceView DetailsProject Code: TVPGBE122
Project Title:Accuracy-Configurable Radix-4 Adder with a Dynamic Output Modification SchemeView DetailsProject Code: TVPGBE110
Project Title:A Low-Power Timing-Error-Tolerant Circuit by Controlling a ClockView DetailsProject Code: TVPGBE118
Project Title:Performance Analysis of Full Adder based on Domino Logic TechniqueView DetailsProject Code: TVPGBE115
Project Title:Design of Two Stage Operational Amplifier and Implementation of Flash ADCLow Power VLSI| Cadence EDA| Tanner EDA
View DetailsProject Code: TVPGBE113
Project Title:BTI and Soft-Error Tolerant Voltage Bootstrapped Schmitt Trigger CircuitView DetailsProject Code: TVPGBE121
Project Title:A Very-Low-Voltage Frequency Divider in Folded MOS Current Mode Logic With Complementary n- and p-type Flip-FlopsView DetailsProject Code: TVREBE19_17
Project Title:Parametric and Functional Degradation Analysis of Complete 14-nm FinFET SRAMView Details Items per page:
1 – 10 of 10
S.no | Project Code | Project Name | Action |
|---|---|---|---|
| 1 | TVPGBE124 | Novel Ternary Adder and Multiplier Designs Without Using Decoders or E... | |
| 2 | TVPGBE123 | Comparative Analysis of Memristor Models with a Window Function Descri... | |
| 3 | TVPGBE122 | Accuracy-Configurable Radix-4 Adder with a Dynamic Output Modification... | |
| 4 | TVPGBE110 | A Low-Power Timing-Error-Tolerant Circuit by Controlling a Clock | |
| 5 | TVPGBE120 | TIQ flash ADC with threshold compensation | |
| 6 | TVPGBE118 | Performance Analysis of Full Adder based on Domino Logic Technique | |
| 7 | TVPGBE115 | Design of Two Stage Operational Amplifier and Implementation of Flash ... | |
| 8 | TVPGBE113 | BTI and Soft-Error Tolerant Voltage Bootstrapped Schmitt Trigger Circu... | |
| 9 | TVPGBE121 | A Very-Low-Voltage Frequency Divider in Folded MOS Current Mode Logic ... | |
| 10 | TVREBE19_17 | Parametric and Functional Degradation Analysis of Complete 14-nm FinFE... |
Items per page:
1 – 10 of 10
Project Code: TVPGBE124
Project Title:Novel Ternary Adder and Multiplier Designs Without Using Decoders or EncodersView DetailsProject Code: TVPGBE123
Project Title:Comparative Analysis of Memristor Models with a Window Function Described in LTspiceView DetailsProject Code: TVPGBE122
Project Title:Accuracy-Configurable Radix-4 Adder with a Dynamic Output Modification SchemeView DetailsProject Code: TVPGBE110
Project Title:A Low-Power Timing-Error-Tolerant Circuit by Controlling a ClockView DetailsProject Code: TVPGBE118
Project Title:Performance Analysis of Full Adder based on Domino Logic TechniqueView DetailsProject Code: TVPGBE115
Project Title:Design of Two Stage Operational Amplifier and Implementation of Flash ADCLow Power VLSI| Cadence EDA| Tanner EDA
View DetailsProject Code: TVPGBE113
Project Title:BTI and Soft-Error Tolerant Voltage Bootstrapped Schmitt Trigger CircuitView DetailsProject Code: TVPGBE121
Project Title:A Very-Low-Voltage Frequency Divider in Folded MOS Current Mode Logic With Complementary n- and p-type Flip-FlopsView DetailsProject Code: TVREBE19_17
Project Title:Parametric and Functional Degradation Analysis of Complete 14-nm FinFET SRAMView Details Items per page:
1 – 10 of 10
S.no | Project Code | Project Name | Action |
|---|---|---|---|
| 1 | TVPGBE124 | Novel Ternary Adder and Multiplier Designs Without Using Decoders or E... | |
| 2 | TVPGBE123 | Comparative Analysis of Memristor Models with a Window Function Descri... | |
| 3 | TVPGBE122 | Accuracy-Configurable Radix-4 Adder with a Dynamic Output Modification... | |
| 4 | TVPGBE110 | A Low-Power Timing-Error-Tolerant Circuit by Controlling a Clock | |
| 5 | TVPGBE120 | TIQ flash ADC with threshold compensation | |
| 6 | TVPGBE118 | Performance Analysis of Full Adder based on Domino Logic Technique | |
| 7 | TVPGBE115 | Design of Two Stage Operational Amplifier and Implementation of Flash ... | |
| 8 | TVPGBE113 | BTI and Soft-Error Tolerant Voltage Bootstrapped Schmitt Trigger Circu... | |
| 9 | TVPGBE121 | A Very-Low-Voltage Frequency Divider in Folded MOS Current Mode Logic ... | |
| 10 | TVREBE19_17 | Parametric and Functional Degradation Analysis of Complete 14-nm FinFE... |
Items per page:
1 – 10 of 10
Project Code: TVPGBE124
Project Title:Novel Ternary Adder and Multiplier Designs Without Using Decoders or EncodersView DetailsProject Code: TVPGBE123
Project Title:Comparative Analysis of Memristor Models with a Window Function Described in LTspiceView DetailsProject Code: TVPGBE122
Project Title:Accuracy-Configurable Radix-4 Adder with a Dynamic Output Modification SchemeView DetailsProject Code: TVPGBE110
Project Title:A Low-Power Timing-Error-Tolerant Circuit by Controlling a ClockView DetailsProject Code: TVPGBE118
Project Title:Performance Analysis of Full Adder based on Domino Logic TechniqueView DetailsProject Code: TVPGBE115
Project Title:Design of Two Stage Operational Amplifier and Implementation of Flash ADCLow Power VLSI| Cadence EDA| Tanner EDA
View DetailsProject Code: TVPGBE113
Project Title:BTI and Soft-Error Tolerant Voltage Bootstrapped Schmitt Trigger CircuitView DetailsProject Code: TVPGBE121
Project Title:A Very-Low-Voltage Frequency Divider in Folded MOS Current Mode Logic With Complementary n- and p-type Flip-FlopsView DetailsProject Code: TVREBE19_17
Project Title:Parametric and Functional Degradation Analysis of Complete 14-nm FinFET SRAMView Details Items per page:
1 – 10 of 10
S.no | Project Code | Project Name | Action |
|---|---|---|---|
| 1 | TVPGBE124 | Novel Ternary Adder and Multiplier Designs Without Using Decoders or E... | |
| 2 | TVPGBE123 | Comparative Analysis of Memristor Models with a Window Function Descri... | |
| 3 | TVPGBE122 | Accuracy-Configurable Radix-4 Adder with a Dynamic Output Modification... | |
| 4 | TVPGBE110 | A Low-Power Timing-Error-Tolerant Circuit by Controlling a Clock | |
| 5 | TVPGBE120 | TIQ flash ADC with threshold compensation | |
| 6 | TVPGBE118 | Performance Analysis of Full Adder based on Domino Logic Technique | |
| 7 | TVPGBE115 | Design of Two Stage Operational Amplifier and Implementation of Flash ... | |
| 8 | TVPGBE113 | BTI and Soft-Error Tolerant Voltage Bootstrapped Schmitt Trigger Circu... | |
| 9 | TVPGBE121 | A Very-Low-Voltage Frequency Divider in Folded MOS Current Mode Logic ... | |
| 10 | TVREBE19_17 | Parametric and Functional Degradation Analysis of Complete 14-nm FinFE... |
Items per page:
1 – 10 of 10
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Disclaimer - Takeoff Edu Group Projects, are not associated or affiliated with IEEE, in any way. The IEEE Projects mentioned here are mentioned in the context of student projects, whose ideas are derived from IEEE publications, and not projects of or by IEEE.
