S.no
Project Code
Project Name
Action
1 TVPGFE336 Design of Optimal Multiplierless FIR Filters With Minimal Number of Ad...
2 TVPGFE335 Low power Dadda multiplier using approximate almost full adder and Maj...
3 TVPGFE334 High-performance multiply-accumulate unit by integrating binary carry ...
4 TVPGFE333 Two Efficient Approximate Unsigned Multipliers by Developing New Confi...
5 TVPGFE332 Simplified Compressor and Encoder Designs for Low-Cost Approximate Rad...
6 TVPGFE331 FPGA-Supported HDL Approach to Implement Reversible Logic Gate-Based ...
7 TVPGFE329 VLSI Design of Pipelined FFT Architecture for DSP Application
Items per page:
1 – 7 of 7
S.no
Project Code
Project Name
Action
1 TVPGFE336 Design of Optimal Multiplierless FIR Filters With Minimal Number of Ad...
2 TVPGFE335 Low power Dadda multiplier using approximate almost full adder and Maj...
3 TVPGFE334 High-performance multiply-accumulate unit by integrating binary carry ...
4 TVPGFE333 Two Efficient Approximate Unsigned Multipliers by Developing New Confi...
5 TVPGFE332 Simplified Compressor and Encoder Designs for Low-Cost Approximate Rad...
6 TVPGFE331 FPGA-Supported HDL Approach to Implement Reversible Logic Gate-Based ...
7 TVPGFE329 VLSI Design of Pipelined FFT Architecture for DSP Application
Items per page:
1 – 7 of 7
S.no
Project Code
Project Name
Action
1 TVPGFE336 Design of Optimal Multiplierless FIR Filters With Minimal Number of Ad...
2 TVPGFE335 Low power Dadda multiplier using approximate almost full adder and Maj...
3 TVPGFE334 High-performance multiply-accumulate unit by integrating binary carry ...
4 TVPGFE333 Two Efficient Approximate Unsigned Multipliers by Developing New Confi...
5 TVPGFE332 Simplified Compressor and Encoder Designs for Low-Cost Approximate Rad...
6 TVPGFE331 FPGA-Supported HDL Approach to Implement Reversible Logic Gate-Based ...
7 TVPGFE329 VLSI Design of Pipelined FFT Architecture for DSP Application
Items per page:
1 – 7 of 7

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