Virtex 7 FPGA Implementation of 256 Bit Key AES Algorithm with Key Schedule and Sub Bytes Block Optimization

Also Available Domains Communications and Crypto Core|Xilinx Vivado|Xilinx ISE

Project Code :TVPGTO658

Objective

The main objective of this paper is to improve the security by extending the cipher key size into 256 bit key AES algorithm and applied selective transformation for optimization.

Abstract

Cryptography is associated with the process of converting ordinary plain text into ambiguous text and vice versa. Hardware Security plays a major role in most of the applications which include net banking, e-commerce, military, satellite, wireless communications, electronic gadgets, digital image processing, etc. There are three types of cryptographic techniques; Symmetric key cryptography, Hash functions and Public key cryptography. Symmetric key algorithms namely Advanced Encryption Standard (AES), and Data Encryption Standard use the same key for encryption and decryption. It is much faster, easy to implement and requires less processing power. In this paper we are proposing 256-bit AES algorithm is highly optimized in Key schedule and Sub bytes blocks, for Area and Power. The optimization has been done by reusing the S-box block. We are optimizing the algorithm with a new approach where internal operations are 32-bit operations, as compared to 128-bit operations. The proposed implementation helps in re-using the same hardware in a pipelined fashion which results in an area reduction by using slice registers. This in turn results in a power reduction in a FPGA implementation. The throughput (Mbps) of the proposed implementation using Virtex-7 (xc7vx485tffg1157) FPGA improved.

NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.

Block Diagram

Specifications

Software Requirements:

· Xilinx ISE Tool /Xilinx Vivado

· HDL: Verilog

Hardware Requirements:

· Microsoft® Windows XP,

· Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support

· 512 MB RAM

· 100 MB of available disk space

Learning Outcomes

Basics of Digital Electronics
FPGA design Flow
Introduction to Verilog Coding
Different modeling styles in Verilog

o Data Flow modeling

o Structural modeling

o Behavioral modeling

o Mixed level modeling

Concept of Cryptography systems
Importance of Crypto systems
Drawbacks of existing methods
Introduction to Advanced Encryption standard (AES)
Knowledge on pipelining concept
Knowledge on Symmetric, Asymmetric and Hash functions
Applications of AES in real time
Scope of AES concept in today’s world
Applications in real time

· Xilinx ISE 14.7/Xilinx Vivado for design and simulation

· Generation of Netlist

· Solution providing for real time problems

· Project Development Skills:

o Problem Analysis Skills

o Problem Solving Skills

o Logical Skills

o Designing Skills

o Testing Skills

o Debugging Skills

o Presentation Skills

o Thesis Writing Skills

Demo Video

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