Virtex 7 FPGA Implementation of 256 Bit Key AES Algorithm with Key Schedule and Sub Bytes Block Optimization

Information security has a major role in the development next generation communication system, where more randomization in the secret key is required for improved security without adding any complexity over existing cryptography algorithms. In the recent years Symmetric key algorithms like Advanced Encryption Standard (AES) is widely used in many network security applications. In this paper we are proposing 256-bit AES algorithm is highly optimized in Key schedule and Sub bytes blocks, for Area and Power. The optimization has been done by reusing the S-box block. We are optimizing the algorithm with a new approach where internal operations are 32-bit operations, as compared to 128-bit operations. The proposed implementation helps in re-using the same hardware in a pipelined fashion which results in an area reduction by using slice registers. This in turn results in a power reduction in a FPGA implementation. The throughput (Mbps) of the proposed implementation using Virtex-7 (xc7vx485tffg1157) FPGA improved.

Keywords: Advanced Encryption Standard (AES), FPGA, LUT (Look up table), Mbps (megabit per second), sub (sub bytes), shift (shift rows), mix (mix column), add (add round key).