Performance Analysis of Full Adder based on Domino Logic Technique

In modern VLSI area efficient devices are most used because most of the devices are becoming portable. The Domino logic technique is often employed in designing the area efficient and high-speed devices. Domino  CMOS  logic  gates  allow  a  significant  reduction  in  number  of transistors  required  to  realize  any  complex  Boolean  function. In this research paper, one- bit full adder circuit using CMOS based logic and domino- based logic on Tanner EDA/Cadence Virtuoso has been designed based on 0.18um technology. This research paper is mainly centralized on the design of area efficient and fast speed devices. This work evaluates the performance CMOS and Domino logic based on full adder circuit in terms of delay and power consumption.