Also Available Domains Low Power VLSI|Cadence EDA
In this project, an energy-ef?cient retentive True Single-Phase-Clocked (TSPC) FF is proposed. With the employment of input-aware pre charge scheme, the proposed TSPC FF pre charge only when necessary. By adopting this technique, power consumption is minimized.
In this Project, an energy-efficient retentive true single-phase-clocked (TSPC) FF is proposed.As basic components, optimizing power consumption of flip-flops (FFs) can significantly reduce the power of digital systems. With the employment of input-aware precharge scheme, the proposed TSPC FF precharges only when necessary. In addition, floating node analysis and transistor level optimization are employed to further ensure the high energy efficiency of the FF without significantly increasing the area. Later, the flipflop is modified by adding SET, RESET ,scan inputs and Finally a soft error tolerant Flipflop is designed. The proposed designs are implemented in Tanner EDA using 45nm technology file.
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