Project Code :TVPGTO718
Abstract
In this project, a signed multiplier with
different adders is implemented. Multipliers are the basic circuits in various
applications. In this a signed multiplier is designer as unsigned multiplier
limits the implementation of signed multiplication. In the reduction process,
adders are implemented to obtain final product. Various adders such as CLA,
CSA, BKA, HCA are implemented and a comparative analysis of multiplies by using
these adders is performed. The synthesis of the implemented designs shows that
by using various adders a tradeoff has been established between area and delay.
NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.
Block Diagram
Specifications
Software Requirements:
- Xilinx Vivado Tool
- HDL: Verilog
Hardware Requirements:
- Microsoft® Windows XP
- Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support
- 512 MB RAM
- 100 MB of available disk space
Learning Outcomes
- Basics of Digital Electronics
- VLSI design Flow
- Introduction to Verilog Coding
- Different modeling styles in Verilog
- Data Flow modeling
- Structural modeling
- Behavioral modeling
- Mixed level modeling
- Introduction to multiplication
- Knowledge on parallel prefix adders
- Different adders such as RCA,CLA,CSA etc
- Knowledge on unsigned multiplication
- Knowledge on signed multiplication
- Applications in real time
- Xilinx ISE 14.7/Xilinx Vivado for design and simulation
- Generation of Netlist
- Solution providing for real time problems
- Project Development Skills:
- Problem Analysis Skills
- Problem Solving Skills
- Logical Skills
- Designing Skills
- Testing Skills
- Debugging Skills
- Presentation Skills
- Thesis Writing Skills