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The main objective of this paper is to minimize the delay and power by implementing the Bi-Directional shift register with 2PASCL Adiabatic logic.
In this paper, we are presenting Bi-directional shift register using adiabatic logic. There are different types of adiabatic logic circuit used for low power consumption. The comparative power consumption of adiabatic logic using Two phase Adiabatic Static Clocked logic is proposed here. In digital design flip flops are the main components responsible for storing in all SOCs. The proposed design exhibits less power and high speed over existing designs. A lot of research has been done on the adiabatic logic based designs and our design leads better results. The designs are simulated in 180nm CMOS Technology.
Keywords: Adiabatic Logic, shift registers, Bi-directional shift register, D Flipflop, 2PASCL.
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