High-Speed Area-Efficient VLSI Architecture of Three-Operand Binary Adder

Also Available Domains Arithmetic Core|Xilinx ISE

Project Code :TVPGTO384

Objective

In this project, a high-speed area-efficient adder technique is proposed to perform the three operands binary addition for efficient computation of modular arithmetic used in cryptography and PRBG applications

Abstract

Three-operand binary adder is the basic functional unit to perform the modular arithmetic in various cryptography and Pseudo Random Bit Generator (PRBG) algorithms and also used in many applications. Carry Save Adder (CS3A) is the widely used technique to perform the three-operand addition.

In carry save adder at final stage uses ripple carry adder which will cause large critical path delay. Moreover, a parallel prefix two-operand adder such as Han-Carlson Adder (HCA) can also be used for three-operand addition that significantly reduces the critical path delay with more area complexity.

Hence, a new high-speed and area-efficient adder architecture is proposed using pre-compute bitwise addition followed by carry prefix computation logic to perform the three-operand binary addition that consumes substantially less area and less delay. The effectiveness of the proposed design is synthesized and simulated using Xilinx Vivado software.

Keywords: Arithmetic Circuits, Three-operand adder, Carry Save Adder (CSA), Han-Carlson Adder (HCA)

NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.

Block Diagram

Specifications

Software Requirements:

Xilinx Vivado
HDL: Verilog

Hardware Requirements:

Microsoft® Windows XP
Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support
512 MB RAM
100 MB of available disk space

Learning Outcomes

Basics of Digital Electronics
FPGA design Flow
Introduction to Verilog Coding
Different modeling styles in Verilog

Data Flow modeling
Structural modeling
Behavioral modeling
Mixed level modeling

Introduction to Arithmetic Circuits
Knowledge on various adders

Carry save adder
Parallel prefix adders

Drawbacks of different adders
Design of various adders such as CSA, HCA etc..
How to design High Speed, low power and area efficient adder circuits
Scope of adders in today’s world
Applications in real time
Xilinx Vivado for design and simulation
Generation of Netlist
Solution providing for real time problems
Project Development Skills:

Problem Analysis Skills
Problem Solving Skills
Logical Skills
Designing Skills
Testing Skills
Debugging Skills
Presentation Skills
Thesis Writing Skills

Demo Video

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Tools

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Xilinx Vivado
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Others

Matlab Interfacing