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This paper presents the area efficient N-bit digital comparator and it was designed with the help of two different modules which are comparison evaluation modules (CEM) and the second module is the final module (FM).
In this project, an area-efficient N-bit digital comparator with high operating speed and low-power dissipation is proposed. The proposed comparator structure consists of two separate modules. The first module is the Comparison Evaluation Module (CEM) and the second module is the Final Module (FM). Independent from the input bit widths, CEM involve the regular structure of repeated logic cells used for implementing parallel prefix tree structure. The FM validates the final comparison based on results obtained from the CEM. The design is implemented using Cadence Virtuoso in 180nm technology.
Keywords: N-bit digital comparator, Comparison Evaluation Module (CEM), Final Module (FM).
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