High Performance Reconfigurable Viterbi Decoder Design for Multi-Standard Receiver

Also Available Domains Xilinx Vivado

Project Code :TVPGTO790

Abstract

This paper presents an improved design of reconfigurable infinite impulse response (IIR) filter that can be widely used in real-time applications. The proposed IIR design is realized by parallel–pipeline-based finite impulse response (FIR) filter. The FIR filters have excellent characteristics such as high stability, linear phase response and fewer finite precision errors. Hence, FIR-based IIR design is more attractive and selective in signal processing. In addition, the other two modern techniques such as look-ahead and two-level pipeline IIR filter designs are also discussed. The implementation results show that the proposed FIR-based IIR design yields better performance in terms of hardware utilization, higher operating speed and lower power consumption compared to conventional IIR filter

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Specifications

Software Requirements:

·         Xilinx Vivado 2018.3

·         HDL: Verilog

Learning Outcomes

Learning Outcomes:

  • Basics of Digital Electronics
  • VLSI design Flow
  • Introduction to Verilog Coding
  • Different modeling styles in Verilog

o   Data Flow modeling

o   Structural modeling

o   Behavioral modeling

o   Mixed level modeling

  • Introduction to Arithmetic circuits
  • Knowledge on types of adder circuits
  • Different multipliers
  • Knowledge on IIR
  • Applications in real time

·         Xilinx ISE 14.7/Xilinx Vivado for design and simulation

·         Generation of Netlist

·         Solution providing for real time problems

·         Project Development Skills:

o   Problem Analysis Skills

o   Problem Solving Skills

o   Logical Skills

o   Designing Skills

o   Testing Skills

o   Debugging Skills

o   Presentation Skills

o   Thesis Writing Skills

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