Glitch Free Combinational Clock Gating Approach in Nanometer VLSI Circuits

Project Code :TVMAFE182


Low power design is gaining prominence due to the increasing need of battery operated portable devices with high computing capability. It is the critical issue in ASIC design, as featured size is scaled down. The reliability of integrated circuit depends on the heat dissipated in the circuit. A large fraction of the power consumed is due to the clock distribution network and the high switching activity at the nodes. Clock Gating is the well-known power-saving technique used to reduce the clock power. To save power, clock gating refers to triggering the clocks in a logic block only when there is work to be done. Every unit on the chip has a power reduction plan, and almost every Functional Unit Block (FUB) contains clock gating logic. In this paper, we explain the way of Glitch reduction for ISCAS 85 bench mark circuits using combinational clock gating principle. The functionality of bench mark circuits are verified using Xilinx   with RTL compiler.

NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.


Hardware requirement

             Processor               -    Pentium –III


Speed                                -    1.1 GHz

RAM                                 -    1 GB (min)

Hard Disk                          -   40 GB

Floppy Drive                     -    1.44 MB

Key Board                         -    Standard Windows Keyboard

Mouse                                -    Two or Three Button Mouse

Monitor                              -    SVGA


Software requirements

v  Operating System            :Windows95/98/2000/XP/Windows7


v  Front End                          :   Modelsim 6.3 for Debugging and Xilinx 14.3 for                     Synthesis and Hard Ware Implementation


v  This software’s where Verilog source code can be used for design implementation.


Learning Outcomes

Basics of Digital Electronics and Verilog.

Demo Video

Request Video

Related Projects

Final year projects