Energy-Quality Scalable Design Space Exploration of Approximate FFT Hardware Architectures

This paper presents a comprehensive design space exploration for boosting energy efficiency of a fast Fourier transform (FFT) VLSI accelerator, exploiting several approximate multipliers (Ax M) combined with approximate adder (Ax A) circuits. The FFT hardware herein presented consists of a fixed-point sequential architecture using a radix-2 butterfly with decimation in time. We explore a set of Ax Ms – namely Dynamic Range Unbiased (DRUM), Rounding-based Approximate (Ro BA), leading one Bit-based Approximate (Lo BA), and Truncated approach – jointly with the LOA, ETA-I, Copy A, Copy B, Trunc0, Trunc1 approximate adders. The approximate arithmetic operators are used in the butterfly kernel with exploration of the approximation levels (for the L and K least-significant bits, respectively, for the Ax M and Ax A), aiming at discovering the most energy-efficient configuration under a design-time QoR constraint. The mean square error and peak signal-to-noise ratio metrics define which approximate levels combining L and K variations will enable the FFT to process signals to generate spectrograms without significant losses. Our results show that the Lo BA multiplier with L=8 together with the LOA, Trunc1 and Trunc0, at different approximation levels, provide most energy savings with controllable quality degradation, presenting a minimum decrease of 20.2% in power dissipation without degrading the spectrogram generation quality.