Efficient FIR Filter Design using Booth Multiplier for VLSI Applications

The most important criteria for the design and implementation of DSP processor is area optimization and reduction in power consumption. The fundamental block for the design and implementation of the DSP processor is the Finite Impulse Response Filter. The Finite Impulse Response (FIR) Filter consists of three basic modules which are adder blocks, flip flops and multiplier blocks .The performance of the FIR Filter is largely influenced by the multiplier, which is the slowest block out of all. In this paper, the Finite Impulse Response Filter has been proposed using two different multipliers namely Array multiplier and Booth Multiplier and both the proposed FIR filters have been compared for various parameters. The proposed filters are designed using Verilog HDL and is implemented using Xilinx 14.7 ISE tools. An improvement has been obtained both in terms of area and delay. Also low power consumption and reduction in terms of delay and operational frequency of the booth multiplier makes it highly suitable for the designing of the FIR Filter for low voltage and low power VLSI applications.