Also Available Domains Low Power VLSI|Tanner EDA
The main objective of this work is to reduce power for Voltage level shifter. The proposed Current limiter circuit is designed using 130nm CMOS technology to perform the voltage level shifting from 0.15V to 1.25V.
In this project, a multi supply voltage Level Shifter technique is designed to enhance the performance. Level shifters (LSs) are the interfacing circuits that allow different voltage domains to be interfaced. Level Shifter satisfies the requirements of Power, Delay, and Voltage level shifting requirements of current IOT applications. The proposed LS implemented using 45nm technology in tanner tool. Simulation results show that the Proposed Level shifter shows better results in terms of delay and power. The proposed design is implemented using 180nm technology in Cadence Virtuoso.
Keywords: Current limiter, Delay, IOT application, Level Shifter.
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