Design and Performance Analysis of Various 32-bit Hybrid Adders using Verilog

Also Available Domains Xilinx Vivado|Xilinx ISE

Project Code :TVMAFE514

Objective

The main objective of this paper is to implementation of different type of 32-bit VLSI adders will be done using differing types of combination of adders and logic.

Abstract

Area, Power and Delay optimizations are the challenges in current digital IC design. Processors which are being currently used require adder units. In this work, different type of 32-bit VLSI adders will be studied and their design implementation will be done. Some of the adders were designed using 3-2 compressor. Some of the 32-bit hybrid adders is proposed by using differing types of combination of adders and logic. The combination includes parallel prefix adders like Kogge-Stone adder (KSA), Brent-Kung adder (BKA), Ladner-Fischer adder (LFA) and Han-Carlson adder (HCA). Two 64-bit hybrid adders is designed by analyzing the performance of the 32-bit designed hybrid adders and by selecting the best 32-bit adders. Analysis of the adder performance can be done in terms of Area (Number of LUT s), Delay (ns) and Power (W) analysis is performed with the help of Xilinx ISE 14.7/Xilinx Vivado2018.3.

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Block Diagram

Specifications

Software Requirements:

· Xilinx ISE14.7 suite/Xilinx Vivado2018.3.

· HDL: Verilog.

Hardware Requirements:

o Microsoft® Windows XP.

o Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support.

o 512 MB RAM.

o 100 MB of available disk space.

Learning Outcomes

· Basics of Digital Electronics.

· Concept of binary addition.

· Different types of binary adders.

· Introduction to Verilog Coding.

· Different modeling styles in Verilog.

· Data Flow modeling.

· Structural modeling.

· Behavioral modeling.

· Mixed level modeling.

· Introduction to adders design.

· About hybrid addition process.

· Knowledge on propagation of sum and carry.

· Knowledge on adders.

· About approximation computing.

· Applications in real time.

· Xilinx ISE14.7 suite / Xilinx Vivado2018.3 for design and simulation.

· Generation of Netlist.

· Solution providing for real time problems.

· Project Development Skills:

o Problem Analysis Skills.

o Problem Solving Skills.

o Logical Skills.

o Designing Skills.

o Testing Skills.

o Debugging Skills.

o Presentation Skills.

o Thesis Writing Skills.

Demo Video

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Front End Domains

Cadence EDA
Finite State Machines
DSP Core
Testing
Nano Technology
Communications
Arithmetic Core

Back End Domains

Cadence EDA
Low Power VLSI
Transistor Logic
Core Memories

Tools

H-Spice
FPGA
QCA
Xilinx Vivado
Xilinx ISE
Tanner EDA
LT-Spice
Cadence EDA

Others

Matlab Interfacing

H-Spice

LT-Spice